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TEA5761UK

Low voltage single-chip FM stereo radio

1. General description

The TEA5761UK is a single-chip electronically tuned FM stereo radio for low-voltage applications with fully integrated IF selectivity and demodulation.

The radio is completely adjustment free and only requires a minimum of small and low cost external components. The radio can tune to the European, US and Japanese

FM bands. The radio does not meet all of the requirements of EN55020; a trade off has been implemented to achieve the following features.

2. Features

High sensitivity due to integrated low noise RF input ampli?er

FM mixer for conversion of the US and Europe FM band (87.5 MHz to 108 MHz) and Japanese FM band (76 MHz to 90 MHz) to IF

Preset tuning to receive Japanese TV audio up to 108 MHz, raster 100 kHz

Auto search tuning, 100 kHz grid

RF automatic gain control circuit

LC tuner oscillator operating with one low-cost chip inductor; no need for external varicap

Fully integrated FM IF selectivity

Fully integrated FM demodulator; no external discriminator

Crystal oscillator at 32768 Hz, or external reference frequency at 32768 Hz

PLL synthesizer tuning system

IF counter; 7-bit output via the I2C-bus

Level detector; 4-bit level information output via the I2C-bus

Soft mute: signal dependent mute function

Mono/stereo blend: gradual change from mono to stereo, depending on signal; Stereo Noise Cancelling (SNC)

Soft mute and SNC can be switched off via the I2C-bus

Adjustment-free stereo decoder

I2C-bus interface

Autonomous search tuning function

Standby mode

MPX output

One software programmable port

Interrupt ?ag

3.Applications

FM stereo radio

4.Quick reference data

Table 1: Quick reference data

VCCA = VCCD = 2.7 V; Tamb = 25 °C; unless otherwise speci?ed.The listed parameters are valid when a crystal is used that meets the requirements as stated in Table 31.

Table 1: Quick reference data …continued

VCCA = VCCD = 2.7 V; Tamb = 25 °C; unless otherwise speci?ed.The listed parameters are valid when a crystal is used that meets the requirements as stated in Table 31.

and L = 0; fmod = 1 kHz; bit MST = 0; bit SNC = 1; Baud = 300 Hz to 15 kHz

VRF = 1 mV; Df = 75 kHz; fmod = 1 kHz; - 0.4 1 % L = R; TCdeem = 75 ms; Baud = 300 Hz to

15 kHz

[1]Crystal in?uence not included.

[2]Low-side and high-side selectivity can be measured by changing the mixer LO injection from high-side to low-side.

5. Ordering information

Table 2: Ordering information

7.Pinning information

7.1Pinning

001aab488

Transparent top view

Fig 2. Pin con?guration of WLCSP34 package

7.2 Pin description

Table 3: Pin description

8.Functional description

8.1Low noise RF ampli?er

The LNA input impedance together with the LC RF input circuit de?nes an FM band ?lter. The gain of the LNA is controlled by the RF AGC circuit.

8.2 I/Q mixer 1st FM

The FM quadrature mixer converts FM RF (76 MHz to 108 MHz) to IF.

8.3 VCO

The LC tuned VCO provides the Local Oscillator (LO) signal for the FM quadrature mixer. The VCO frequency range is from 150 MHz to 217 MHz. No external varactor is required.

8.4 Crystal oscillator

The crystal oscillator can operate with a 32.768 kHz clock crystal or via an external 32.768 kHz reference clock source connected to pin FREQIN. Selection between a reference clock or a reference crystal can be done by software programming via the I2C-bus. When a clock crystal is used, pin FREQIN must be left open-circuit, or when external clocking is used, there should be no crystal connected to pin XTAL.

The temperature drift of 32.768 kHz clock crystals limits the operational temperature range. The preferred crystal speci?cations are given in Table 31.

The crystal oscillator generates the reference frequency for:

?Synthesizer PLL tuning system

?Timing for the IF counter

?Free running frequency adjustment of the stereo decoder VCO

?Center frequency adjustment of the IF ?lters

8.5 PLL tuning system

The PLL synthesizer tuning system is suitable to operate with a 32.768 kHz reference frequency generated by the crystal oscillator or a reference clock of 32.768 kHz fed into the TEA5761UK. To tune the radio to the required frequency requires the PLL word to be calculated and then programmed to the register. The PLL word is 14 bits long; see

Table 12 and Table 13. Calculation of this 14-bit word can be done as follows.

Formula for high-side injection:

Formula for low-side injection:

where:

NDEC = decimal value of PLL word fRF = wanted tuning frequency (Hz)

fIF = intermediate frequency of 225 kHz fref = reference frequency of 32.768 kHz

Example for receiving a channel at 100.1 MHz:

(1)

(2)

(3)

The result found using Equation 1 or Equation 2 must always be rounded to the lowest integer value. If rounded down to the lowest integer value of NDEC = 12246, the PLL word becomes 2FD6h.

This value can be written to register FRQSET via the I2C-bus and the TEA5761UK will then start an autonomous search at this frequency or go to a preset channel at this frequency. When the application is built according to the application diagram (see Figure 13) and with the preferred components, the PLL will settle to the new frequency within 40 ms.

The PLL is triggered by writing to any one of the bytes FRQSETMSB, FRQSETLSB,

TNCTRL1, TNCTRL2, TESTBITS, TESTMODE.

Accurate validation of the PLL locking on the new frequency can take 40 ms. When a lock is detected bit LD is set.

8.6 Band limits

The TEA5761UK can be switched to the Japanese FM band or to the US and Europe FM band. Setting bit BLIM to logic 0 the band range is 87.5 MHz to 108 MHz; setting bit BLIM to logic 1 selects the Japanese band range of 76 MHz to 90 MHz.

8.7 RF AGC

The RF AGC prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. The RF AGC is on by default and can be turned off via the I2C-bus.

The TEA5761UK also has an in-band AGC to prevent overloading by the wanted channel. The in-band AGC is always turned on.

8.8 Local or long distance receive

If bit LDX = 1, the LNA gain is reduced by 6 dB to prevent distortion when a transmitter is very near. If bit LDX = 0, the LNA gain is normal to receive long distance (DX) stations.

8.9 IF ?lter

A fully integrated IF ?lter with a center frequency of 225 kHz is built-in.

8.10 FM demodulator

The FM quadrature demodulator has an integrated resonator to perform the phase shift of the IF signal.

8.11 IF counter

The received signal is mixed to an IF of 225 kHz. The result of the mixing is counted. A good IF count result indicates that the radio is tuned to a valid channel instead of an image or a channel with much interference. The IF counter outputs a 7-bit count result via the I2C-bus. The IF counter is continuously active and can be read at any time via the I2C-bus. It also activates a ?ag when the IF count result is outside the IF count valid result window; see Section 9.2.2. The IF count period can be set to 1.953 ms or 15.625 ms by bit IFCTC.

8.12 Voltage level generator and analog-to-digital converter

The voltage level indicates the ?eld strength received by the antenna. The voltage level is analog-to-digital converted to a 4-bit word and output via the I2C-bus. The ADC level is continuously active and can be read at any time via the I2C-bus. It also activates a ?ag when the voltage level falls under a prede?ned selectable threshold. Bit LHSW allows either large or small hysteresis steps to be chosen; see Table 21 and Section 9.2.3.

8.13 Mute

8.13.1Soft mute

The low-pass ?ltered level voltage drives the soft mute attenuator at low RF input levels: the audio output is faded and hence also the noise (curves 1 and 2 of Figure 12).

The soft mute function can also be toggled via the I2C-bus, using bit SMUTE.

8.13.2Hard mute

The audio outputs VAFL and VAFR can be hard muted by bit MU in byte TNCTRL2 which means they are put into 3-state. This can also be done by setting bits Left Hard Mute (LHM) or Right Hard Mute (RHM) in byte TESTBITS, which allows either one or both channels to be muted and forces the TEA5761UK to Mono mode. When the TEA5761UK is in Standby mode the audio outputs are hard muted.

8.13.3Audio frequency mute

The audio signal is muted by setting bit AFM of the TNCTRL1 register to logic 1. In the soft mute attenuator the audio signal is blocked and so pins VAFL and VAFR will be at their DC biasing point with no signal.

The audio is automatically muted during a preset as shown in the ?owchart of Figure 3. When the audio must be muted during Search mode, it is done by setting bit AFM to logic 1 before the search action and resetting it to logic 0 afterwards.

Table 4: Speci?cation of Mute modes

8.14 MPX decoder

The PLL stereo decoder is adjustment free. It can be switched to mono via the I2C-bus.

8.15 Signal dependent mono/stereo blend (stereo noise cancellation)

If the RF input level decreases, the MPX decoder blends from stereo to mono to limit the output noise. The continuous mono-to-stereo blend can also be programmed via the I2C-bus to an RF level dependent switched mono-to-stereo transition. Stereo noise cancellation can be switched off via the I2C-bus by bit SNC.

8.16 Software programmable port

The software programmable port (CMOS output) can be addressed via the I2C-bus:

?Bit SWPM = 1: port functions as the output for bit FRRFLAG.

?Bit SWPM = 0: port outputs the level corresponding to bit SWP.

In Test mode, the software port outputs signals according to Table 23. Test mode is selected by setting bit TM of byte TESTMODE to logic 1.

The programmed output status of the software port remains, independent of bit PUPD; see Section 8.17.

8.17 Standby mode

The radio can be put into Standby mode by Power-Up / Power-Down bit PUPD. In this mode, the FM part can be turned off. The TEA5761UK is still accessible via the I2C-bus but takes only very low power from the supply. In Standby mode, the audio outputs are hard muted.

When the supply voltages VCCA and VCCD are made 0 V and VREFDIG = HIGH, all inputs and outputs, the audio outputs and the reference clock input are in high-impedance state.

The power supplies can be switched on in any order.

8.18 Power-on reset

After start-up of VCCA and VCCD a power-on reset circuit will generate a reset pulse and the registers will be set to their default values. The power-on reset is effectively generated by VCCD.

At power-on reset, the mute is set and all other bits are set to the reset value as given in Table 9. To initialize the TEA5761UK all bytes have to be transferred.

8.19 I2C-bus interface

The I2C-bus interface operates with a maximum clock frequency of 400 kHz.

When, during operation, the signal on pin BUSENABLE is toggled, the device will not generate an I2C-bus acknowledge bit on the ?rst following I2C-bus transmission. It is then necessary to send either the I2C-bus address two times prior to the complete transmission or send the complete I2C-bus transmission twice. After this, the I2C-bus communication is restored in the normal behavior. Now an I2C-bus acknowledge is generated on each transmitted byte again.

8.20 Auto search and Preset mode

8.20.1Search mode

In Search mode the IC can search channels automatically; see Figure 3.

When the INTX signal is used as an interrupt to the microcontroller to indicate a search stop, the INTMSK register must be reset and only bit FRRMSK must be set. In this way the microcontroller will only be interrupted when the search or preset algorithm is ready.

Search mode is initiated by setting bit SM in byte FRQSETMSB to logic 1. The search direction is set by bit SUD; bit SUD = 0 (search down), bit SUD = 1 (search up). The tuner starts searching at the frequency from where it is or at a start frequency set in bytes FRQSETLSB and FRQSETMSB. The Search Stop Level (SSL) bits de?ne the ?eld strength level at which a desired channel is detected. The tuner will stop on a channel with a ?eld strength equal to or higher than this reference level and then checks the IF frequency; when both are valid, the search stops. If the level check or the IF count fails, the search continues. If no channels are found, the TEA5761UK stops searching when it has reached the band limit, setting bit BLFLAG HIGH. A search always stops when the FRRFLAG is set and on the occurrence of a hardware interrupt, this procedure is shown in Figure 3.

The search algorithm can stop at a frequency that is offset from the IF by up to a maximum of 12 kHz. The maximum offset can be limited to 8 kHz by applying a preset. For optimum tuning, it is recommended that a preset is applied after a search and when the found frequency has an offset that is above 8 kHz.

After this interrupt the TEA5761UK will not update the tuner registers INTREG, FRQCHK and TUNCHK for a period of 15 ms. The state of the TEA5761UK can be checked by reading registers INTREG, FRQCHK and TUNCHK. Table 5 shows the possible states of these registers after an auto search.

8.20.2Preset mode

A preset occurs by setting bit SM to logic 0 and writing a frequency to register FRQSET. The tuner jumps to the selected frequency and sets bit FRRFLAG when it is ready.

After this interrupt the TEA5761UK will not update the tuner registers INTREG, FRQCHK and TUNCHK for a period of 15 ms. The state of the TEA5761UK can be checked by reading registers INTREG, FRQCHK and TUNCHK. Table 5 shows the possible states after a preset.

8.20.3Auto high-side and low-side injection stop switch

When a channel is searched or a preset is done, reception can sometimes be improved when Local Oscillator (LO) injection is done at the other side of the wanted channel.

Bit HLSI toggles the injection of the local oscillator from high-side (bit HLSI = 1) to low-side (bit HLSI = 0). When bit HLSI is toggled, a new PLL setting must be sent to the TEA5761UK.

When bit AHLSI is set to logic 1, the search or preset algorithm will stop after a channel has a valid RSSI level check, but fails the IF count. The microcontroller can now respond by toggling bit HLSI and sending a new PLL value to the tuner.

Fig 4. Switch LO from high-side injection to low-side injection using bit HLSI

8.20.4Muting during search or preset

During a preset the tuner is always muted and is implemented by the algorithm. A search is not muted by default unless bit AFM = 1 or bit AHLSI = 1.

When bit AHLSI = 1 and the tuner stops during a preset or a search because of a wrong IF count, the tuner stays muted; this allows the microcontroller to switch LO injection mode quietly and wait for the new result.

The tuner is always muted if bit AFM = 1 and is independent of a search or a preset. A search can be muted by setting bit AFM to logic 1 before a search is initiated and resetting it to logic 0 when the tuner is ready (only set bit FRRMSK when initiating a search or preset).

All these mute actions are done by blocking the audio signal inside the soft mute attenuator, so the audio output will keep its DC level and stay low-impedance i.e. 50 W (a hard mute set by bit MU will cause a plop).

9.Interrupt handling

9.1 Interrupt register

The ?rst two bytes of the I2C-bus register contain the interrupt masks and the interrupt ?ags. A ?ag is set when it is a logic 1.

The interrupt ?ag register contains the ?ags set according to the behavior outlined in Section 9.2. When these ?ags are set they can also cause pin INTX to go active (hardware interrupt line) depending on the status of the corresponding mask bit in Table 7. A logic 1 in the mask register enables the hardware interrupt for that ?ag.

Hence, it is conceivable that, with all the mask bits cleared, the software could operate in a continuous polling mode that reads the interrupt ?ag register for any bits that may be set.

Interrupt mask bits are always cleared after reading the ?rst two bytes of the interrupt register. This is to control multiple hardware interrupts; see Figure 5.

9.1.1Interrupt clearing

The interrupt ?ag and mask bits are always cleared after:

?they have been read via the I2C-bus

?a power-on reset

9.1.2Timing

The timing sequence for the general operation interrupts is shown in Figure 5 and shows a read access of the interrupt register INTFLAG and a subsequent (though not necessarily immediate) write to the mask register INTMSK. It also indicates the two key timing points A and B1 or B2.

If an interrupt event occurs while the register is being accessed (after point A), it must be held until after the mask register is cleared at the end of the read operation (point B2).

Point A is after the R/W bit has been decoded and point B2 is where the acknowledge has been received from the master after the ?rst two bytes have been sent.

The LOW time for the INTX line (tL) has a maximum value speci?ed in Table 30. However, it can be shorter if a read of the INTMSK and INTFLAG registers occurs within tL.

9.1.3Reset

A reset can be performed at any time by a simple read of the interrupt registers (byte0R and byte1R), which automatically clears the interrupt ?ags and masks.

sheet data Product

2006 August 2 — 01 .Rev

44 of 15

13451 750 9397

.reserved rights All .2006 .V.N Electronics Philips Koninklijke ?

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(1)Interrupt events that occur outside of the region A to B1 or B2 set their respective ?ag bits in the normal way immediately and can thus trigger a hardware interrupt if the mask bits are set.

(2)The blocking of interrupts is marked by the region A to B1 or B2, depending on the actual read cycle.

B1 is when only the INTFLAG register is read and a stop condition is received (only INTFLAG is read, so only this will be cleared). B2 is when both registers are read and hence cleared; this is terminated by either an acknowledge or stop bit.

(3)Interrupt events that occur between A and B1 or B2 set their respective ?ags after the mask bits are cleared. This means that in this diagram an interrupt event occurred in period A to B1 or B2, so after period A to B2 the ?ag goes to logic 1.

(4)All interrupt mask bits are cleared after the interrupt ?ag and mask registers are read.

(5)Software writes to the mask register and enables the required mask bits. Any ?ags currently set will then trigger a hardware interrupt.

(6)Pin INTX is set HIGH (inactive) after the interrupt ?ag and mask registers are read.

Fig 5. I2C-bus interrupt sequence, read and write operation

Semiconductors Philips

9.2Interrupt ?ags and behavior

9.2.1Multiple interrupt events

If the interrupt mask register bit is set then the setting of an interrupt ?ag for that bit causes a hardware interrupt (pin INTX goes LOW). If the event occurs again, before the ?ag is cleared, then this does not trigger any further hardware interrupts until that speci?c ?ag is cleared. However, two different events can occur in sequence and generate a sequence of hardware interrupts. A second interrupt can be generated only after the INTMSK byte is read, followed by a write as the ?rst interrupt blocks the input of the INTX one-shot generator.

If subsequent interrupts occur within the INTX LOW period then these do not cause the INTX period to extend beyond its speci?ed maximum period (see Section 9.3).

9.2.2IF frequency ?ag

During automatic frequency search or preset, the FM part of the TEA5761UK performs a check of the received IF frequency. If an incorrect IF frequency is received, it indicates a detuning situation or the presence of either strong interferers or tuning to an image which sets bit IFFLAG in the INTFLAG register. Also a preset to a channel with no signal may result in a wrong IF count value and hence the setting of bit IFFLAG.

When a search or preset is ?nished, bit FRRFLAG will be set to indicate this and an interrupt is generated. The microcontroller can now read the outcome of the registers which will contain the IF count value and the IFFLAG status of the channel it is tuned to.

15 ms after the FRRFLAG ?ag has been set the IF counter will start to run continuously on the tuned frequency and if the conditions for correct frequency are not met then this sets bit IFFLAG in the interrupt register. When bit IFMSK is set this will also cause an interrupt.

Bit IFFLAG is cleared by reading byte0R, or by starting the tuning algorithm.

9.2.3RSSI threshold ?ag

The RSSI level voltage re?ects the ?eld strength received by the antenna. The voltage level is analog-to-digital converted to a 4-bit value and output via the I2C-bus. This 4-bit level value can be compared to a threshold level (see Table 21). The level ADC (which converts the analog value to digital) can be triggered to convert in two ways:

1.During a tuning step, which can be a search or a preset, it is triggered by these algorithms and compares the level with the threshold set by bits SSL[1:0]. Bit LEVFLAG is set if the RSSI level drops below the threshold level set by bits SSL[1:0]; see Table 15. The hardware interrupt is only generated if the corresponding mask bit is set.

2.After a search or a preset, the threshold for comparison is switched to the hysteresis level. The hysteresis level is set by the level bits and can be selected using bit LHSW

(see Table 21). Then it waits 15 ms and the level ADC starts to run automatically and compares the level each 500 ms with this hysteresis level. Bit LEVFLAG is set if the RSSI level drops below the threshold level set by the LH bits; the hardware interrupt is only generated if the corresponding mask bit is set. Bit LHSW allows either a small or a large hysteresis to be selected. When a search or preset is done with the ADC level set to 3 then when the algorithm has ?nished, the threshold level is set to 0. Hence the LEVFLAG will never be set.

Bit LEVFLAG is cleared when the interrupt register INTFLAG is read.

9.2.4Frequency ready ?ag

The frequency ready ?ag bit FRRFLAG is set to logic 1 when the automatic tuning has ?nished a search or preset. The description of this bit is given in Table 5. This bit is cleared when the INTMSK register is read.

9.2.5Band limit ?ag

The band limit bit BLFLAG is set to logic 1 when the automatic tuning has detected the end of the tuning band or when the PLL cannot lock on a certain frequency. This bit is described in Table 5. This bit is cleared when the INTMSK register is read.

9.3Interrupt output

The interrupt line driver is a MOS transistor with a nominal sink current of 380 mA. It is pulled HIGH by an 18 kW resistor connected to pin VREFDIG. The interrupt line can be connected to one other similar device with an interrupt output and an 18 kW pull-up resistor providing a wired-OR function. This allows any of the drivers to pull the interrupt line LOW by sinking the current. When a ?ag is set and not masked it generates an interrupt; see Figure 6.

VCCA

flag(1)

INTX

read INTMSK(2)

write INTMSK(3)

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(1)When ?ag is set, the next interrupts are blocked until INTMSK is read from or written to.

(2)Reading INTMSK clears ?ag, INTMSK and INTX.

(3)Writing INTMSK enables INTX.

Fig 6. Interrupt line behavior

10. I2C-bus interface

The I2C-bus interface is based on The I2C-bus speci?cation, version 2.1 January 2000, expanded by the following de?nitions.

10.1 Write and Read mode

Table 8: I2C-bus transfer description

10.2 Data transfer

Structure of the I2C-bus:

?Slave transceiver

?Subaddresses not used

?Maximum LOW-level input voltage: VIL = 0.3 VVREFDIG

?Minimum HIGH-level input voltage: VIH = 0.7 VVREFDIG

Remark: The I2C-bus operates at a maximum clock rate of 400 kHz. It is not allowed to connect the TEA5761UK to an I2C-bus operating at a higher clock rate.

Data transfer to the TEA5761UK:

?Bit 7 of each byte is considered the MSB and has to be transferred as the ?rst bit of the byte.

?The LSB indicates the write or read action.

?The data becomes valid byte-wise at the appropriate falling edge of the SCL clock.

?A STOP condition after any byte can shorten transmission times. When writing to the transceiver by using the STOP condition before completion of the whole transfer:

The remaining bytes will contain the old information.

If the transfer of a byte is not completed the new bits will be used, but a new tuning cycle will not be started.

I2C-bus activity:

?With bit PUPD the TEA5761UK can be switched in a low current Standby mode. The I2C-bus is then still active.

?When the I2C-bus interface is deactivated, by making pin BUSENABLE LOW and without programmed Standby mode, the TEA5761UK keeps its normal operation, but is isolated from the I2C-bus lines.

?Bus traf?c can be started 10 ms after activating the bus again by making pin BUSENABLE HIGH.

BUS

ENABLE

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tf = fall time of both SDA and SCL signals: 20 + 0.1 Cb < tf < 300 ns, where Cb = total capacitance on bus line in pF. tr = rise time of both SDA and SCL signals: 20 + 0.1 Cb < tr < 300 ns, where Cb = total capacitance on bus line in pF. tHD;STA = hold time (repeated) START condition. After this period, the ?rst clock pulse is generated: > 600 ns.

tHIGH = HIGH period of the SCL clock: > 600 ns.

tSU;STA = setup time for a repeated START condition: > 600 ns. tHD;DAT = data hold time: 300 < tHD;DAT < 900 ns.

Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal.

tSU;DAT = data setup time: tSU;DAT > 100 ns. If ASIC is used in a standard mode I2C-bus system, tSU;DAT > 250 ns. tSU;STO = setup time for STOP condition: > 600 ns.

tBUF = bus free time between a STOP and a START condition: > 600 ns. Cb = capacitive load of one bus line: < 400 pF.

tSU;BUSEN = bus enable setup time: tSU;BUSEN > 10 ms. tHO;BUSEN = bus enable hold time: tHO;BUSEN > 10 ms.

Fig 9. Bus timing diagram

10.3 Register map

Table 9: Register overview

10.4 Byte description

Table 10: INTFLAG - interrupt ?ag byte0R description

[1]This bit does not switch the radio from mono to stereo, this depends on the RF input level as shown in sections ‘Mono stereo blend’ and Mono stereo switched’ in Table 33.

Table 20: TESTBITS - test bits register byte10R and byte5W description

Table 23: Test bits (SWPM = 0)

11. Limiting values

Table 28: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]Human body model (R = 1.5 kW, C = 100 pF).

[2]Charged device model (“JEDEC standard JESD22-C101”).

[3]Machine model (R = 0 W, C = 200 pF).

12. Static characteristics

Table 29: Supply characteristics

The listed parameters are valid when a crystal is used with the requirements stated in Table 31.

[1]Crystal in?uence not included.

Table 30: Control input and output characteristics

VCCA = VCCD = 2.7 V; Tamb = 25 °C; minimum and maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise speci?ed.

Interrupt output: pin INTX [1]

VVREFDIG = 1.65 V; pull-up resistance of

second device connected to INTX is 18 kW, or maximum load current is 100 mA

Table 30: Control input and output characteristics …continued

VCCA = VCCD = 2.7 V; Tamb = 25 °C; minimum and maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise speci?ed.

[1]VVREFDIG 3 1.65 V; Rpu of second device connected to pin INTX is 18 kW ± 20 %.

13. Dynamic characteristics

Table 31: Oscillators, clocks and synthesizer characteristics

VCCA = VCCD = 2.7 V; VVREFDIG = 1.8 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless

otherwise speci?ed; all RF input values are de?ned in potential difference (PD), except when EMF is explicitly stated.

Table 31: Oscillators, clocks and synthesizer characteristics …continued

VCCA = VCCD = 2.7 V; VVREFDIG = 1.8 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless

otherwise speci?ed; all RF input values are de?ned in potential difference (PD), except when EMF is explicitly stated.

Table 32: IF counter characteristics

VCCA = VCCD = 2.7 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise

speci?ed; all RF input values are de?ned in potential difference (PD), except when EMF is explicitly stated.

Table 33: FM signal channel characteristics

VCCA = VCCD = 2.7 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise

speci?ed; all RF input values are de?ned in potential difference (PD), except when EMF is explicitly stated.

Table 33: FM signal channel characteristics …continued

VCCA = VCCD = 2.7 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise

speci?ed; all RF input values are de?ned in potential difference (PD), except when EMF is explicitly stated.

Table 33: FM signal channel characteristics …continued

VCCA = VCCD = 2.7 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise

speci?ed; all RF input values are de?ned in potential difference (PD), except when EMF is explicitly stated.

Table 33: FM signal channel characteristics …continued

VCCA = VCCD = 2.7 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise

speci?ed; all RF input values are de?ned in potential difference (PD), except when EMF is explicitly stated.

[1]Low-side and high-side selectivity can be measured by changing the mixer LO injection from high-side to low-side.

(1)Mono signal: soft mute off, Df = 22.5 kHz.

(2)Noise in Mono mode, soft mute off, Df = 0 kHz.

(3)Total harmonic distortion, Df = 75 kHz.

Fig 10. FM characteristics mono

VRFIN1, VRFIN2 (V)

(1)VAFL signal, modulation left, SNC on, Df = 67.5 kHz; Dfpilot = 6.75 kHz.

(2)VAFR signal, modulation left, SNC on, Df = 67.5 kHz; Dfpilot = 6.75 kHz.

(3)Noise in Stereo mode, SNC on, Df = 0 kHz; Dfpilot = 6.75 kHz.

(4)Total harmonic distortion: Df = 67.5 kHz; Dfpilot = 6.75 kHz.

(5)Noise in Mono mode, SNC off, Df = 0 kHz; Dfpilot = 0 kHz.

Fig 11. FM characteristics stereo

VRF (μVEMF)

(1)Mono signal, soft mute on, Df = 22.5 kHz.

(2)Noise in Mono mode, soft mute on, Df = 0 kHz.

(3)Total harmonic distortion, Df = 100 kHz.

Fig 12. FM characteristics mono, soft mute active and THD at 100 kHz deviation

sheet data Product

2006 August 2 — 01 .Rev

44 of 36

13451 750 9397

.reserved rights All .2006 .V.N Electronics Philips Koninklijke ?

33 nF

Total of 15 external components.

Fig 13. Application diagram

15. Package outline

D B A

bump A1 index area

A2

E A

A1

detail X

16.Soldering

16.1Introduction to soldering WLCSP packages

This text gives a very brief insight to a complex technology. A more in-depth account of soldering WLCSP packages can be found in “AN10365. Application note for wafer level CSPs”. Wave soldering is not suitable for this package.

16.2 Re?ow soldering process

Re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Tp = 260 °C. TL = 217 °C. Tsmin = 150 °C. Tsmax = 200 °C.

tp = 20 s to 40 s.

tsmin to tsmax = 60 s to 180 s.

Time from 25 °C to peak temperature is maximal 8 minutes.

Fig 15. Solder re?ow pro?le

16.2.2Quality of solder joint

A ?ip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. The surface of the joint should be smooth and the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps after re?ow can occur during the re?ow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. No failures have been found to be related to these voids. Solder joint inspection after re?ow can be done with X-ray to monitor defects such as bridging, open circuits and voids.

16.2.3Rework

In general, rework is not recommended. By rework we mean the process of removing the chip from the substrate and replacing it with a new chip. If a chip is removed from the substrate, most solder balls of the chip may be damaged. In that case it is recommended not using the chip again.

Device removal can be done when the substrate is heated until it is certain that all solder joints are molten. The chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. The surface of the substrate should be carefully cleaned and all solder and ?ux residues and/or under?ll removed. When a new chip is placed on the substrate, use the ?ux process instead of solder on the solder lands. Apply ?ux on the bumps at the chip side as well as on the solder pads on the substrate. Place and align the new chip while viewing with a microscope. To re?ow the solder, use the solder pro?le shown in this document.

16.2.4Cleaning

Cleaning can be done after re?ow soldering.

17.References

[1]The I2C-bus speci?cation — version 2.1 January 2000

[2]JESD22-C101JEDEC standard for CDM test

[3]AN10365 — Application note for wafer level CSPs

18.Revision history

Table 36: Revision history

[1]Please consult the most recently issued data sheet before initiating or completing a design.

[2]The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

[3]For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

20. De?nitions

Short-form speci?cation — The data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values de?nition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speci?cation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation.

21. Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Noti?cation (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed.

22. Trademarks

Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners.

I2C-buslogo is a trademark of Koninklijke Philips Electronics N.V.

23. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

24. Contents

? Koninklijke Philips Electronics N.V. 2006

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Date of release: 2 August 2006

Document number: 9397 750 13451

Published in The Netherlands

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